Implementation and Demonstration of 128-channel Theseus Cores Polyphase Filter Bank Receiver Design
Theseus Cores (https://www.theseus-cores.com/) is an open source collection of powerful field programmable gate array (FPGA) designs for digital communications. The polyphase channelizer is a central component of Open Research Institute’s receiver designs. This project implements and demonstrates the Theseus Cores channelizer at 5 GHz.
Our design consists of 128 user channels distributed across 10 MHz in the amateur satellite uplink sub-band.
Theseus Cores blocks are written to use GNU Radio’s Radio Frequency Network on a Chip (RFNoC) framework. This is the way GNU Radio deploys hardware description language code directly to FPGAs in software defined radios (SDR).
This is very necessary and exciting work because the load-balancing act between general purpose processors and increasingly complex and powerful FPGAs is one of the most important architectural challenges currently faced by software designers.
This project takes the Theseus Cores blocks as a starting point. The student will modify and update the blocks and create any other software necessary to achieve the 128-channel demonstration version. The goal is a documented working reference design in GNU Radio.
The process will be document, design, code, and test.
Expected challenges include navigating the RFNoC build process and toolchain installation and learning curve.
The identification and documentation of specific and particular software or hardware bottlenecks in Theseus Cores that prevent deployment of 128 channels in 10 MHz would be a perfectly acceptable work product.
Mentorship from Theseus Cores and experts in polyphase design are available.