Building a 1-Bit Oversampling SDR with not much more than a low cost FPGA
Building a 1-Bit Oversampling SDR with not much more than a low cost FPGA by RTL-SDR Blog
https://www.rtl-sdr.com/building-a-1-bit-oversampling-sdr-with-not-much-more-than-a-low-cost-fpga/ (sourced and republished from RSS feeds)
Thank you to Alberto Garlassi for submitting information about his super low parts home made FPGA software defined radio which is capable of medium wave and shortwave AM reception. What makes this design interesting is that is is created with nothing more than 3 resistors, 1 capacitor, and a low cost 30€ Lattice MachXO2 FPGA dev board.
The design makes use of the FPGA’s LVDS buffer input to implement a direct sampling 1-bit ADC to which a wire antenna is directly connected to. This 1-bit resolution is increased by using an SDR trick that involves superimposing random RF noise onto the desired signal, and oversampling at 80 MHz then decimating down to a 6 kHz bandwidth. This results in an effective ADC resolution of 6-bits, from 1-bit hardware. […continue reading full article]